Skip to content

Interrupt Tutorial

Interrupts - Hardware events Exceptions - Software errors

Interrupt Vector Table are stored in BOOT ROM from 492.

In XSM architecture, interrupts are used to transfer control from unprivileged user program to privileged kernel mode handlers.

XSM supports 3 hardware interrupts.

Interrupt Routines stretch from Page 4 to Page 9. (From 2048, each of size 1024)

Interrupt Type Handler Address (ROM) Preset Value (RAM Start) Function
Timer 493 2048 Used for time-sharing and ensuring no application runs indefinitely.
Disk 494 3072 Signaled when a disk transfer (initiated by load or store) completes.
Console 495 4096 Signaled when the user enters data after an IN instruction.
### Interrupt Handling Procedure (Timer Example)

When an interrupt is triggered (Timer counter reaches zero), the XSM machine performs the following sequence:

  • Save Context: The current Instruction Pointer value of the user program is pushed onto the top of the stack.
  • Vector Check: The IP is set to the value stored in Interrupt Vector Table entry for that interrupt.
  • Mode Switch - The machine switches to Privileged Mode, Address Translation is disabled.
  • Handler Execution - The next instruction is fetched from the result address.

Where is the instruction pointer of the user program pushed?

The instruction pointer is stored in Kernel Stack, and is popped when the execution of the handler is done.

Exception Handling in XSM

Exceptions are synchronous events caused by the user program (e.g., illegal operations or memory access errors). The Exception handler is privileged.

  • Exception Handler Start Address - 1024
  • When an exception occurs, the machine sets the IP to 1024 and switch to privileged mode.
Cause Code (EC Register Value) Exception Type Description
2 Illegal Memory Access The program accesses an address outside its logical address space (PTLR violation) or attempts to write to a page without the Write access bit set.
1 Illegal Instruction The program attempts to execute a non-existent instruction or an instruction with illegal operands (e.g., MOV IP, 4).
3 Arithmetic Exception Division or modulus by zero (e.g., DIV R0, 0).
0 Page Fault The instruction refers to a valid logical page (within PTLR range), but the Valid Bit in the corresponding Page Table Entry (PTE) is set to 0.
Page Fault < Illegal Instruction < Illegal Memory Access < Mathematical Exception
### Page Fault Mechanism

Page Fault enables OS to implement Demand Paging

  • Trigger - A page fault occurs during the Instruction Fetch
  • If the valid bit is 0, the handler allocates the required memory page and sets the valid bit back to 1.
Register Name Relevance Value Stored
EIP Exception IP Always set. The Logical IP of the unprivileged instruction that caused the exception.
EC Exception Cause Always set. A numerical code (0, 1, 2, or 3) indicating the exact type of exception (e.g., 0 for Page Fault).
EPN Exception Page Number Only for Page Faults. The Logical Page Number that caused the page fault.
EMA Exception Memory Address Only for Illegal Memory Access. The illegal memory address the process attempted to access.
The exception handler typically uses these registers to determine the cause and execute privileged routines.

Remember - Instruction Cause Page Memory

Interrupt Vector Table

Interrupt Number (Vector) Purpose IVT Physical Address Preset Handler Address (Value in ROM)
0 Exception Handler 492 1024 (Physical Page 2 start)
1 Timer Interrupt 493 2048 (Physical Page 4 start)
2 Disk Interrupt 494 3072 (Physical Page 6 start)
3 Console Interrupt 495 4096 (Physical Page 8 start)
4 - 18 Software Interrupts (INT n) 496 - 510 Preset values (corresponding to fixed kernel pages for each handler).