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XSM Debugging

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My Knowledge Base

My Knowledge Base
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Artificial Intelligence
Artificial Intelligence
Cloud Computing
Cloud Computing
Compiler Lab
Compiler Lab
- Basics
- Compiler Theory
- LEX and YACC
- Regex
- XSM Execution Environment
- Stage 0
  Stage 0
  - ExpL Compiler: Stage 0 | XSM Execution Environment and Setup
- Stage 1
  Stage 1
  - ExpL Compiler: Stage 1 | Code Generation for Arithmetic Expressions
- Stage 2
  Stage 2
  - ExpL Compiler: Stage 2 | Static Storage Allocation
- Stage 3
  Stage 3
  - Adding Flow Control Statements
- Stage 4
  Stage 4
  - Run Time Data Structures & Storage Allocation
Computer Architecture
Computer Architecture
- Computer Architecture
Computer Networks
Computer Networks
- Address Resolution Protocol
- Applications and Architecture
- Computer Devices
- DNS and HTTP
- Error Detection
- MAC Protocols
- Maximum Data Rate
- Multiple Access Techniques
- Network Devices
- Network Identifiers
- Network Models
- Network Topologies
- Networking Concepts
- Networks
- OSI Model
- Delay
- Portions
- Reliable Transmission and Error Checking
- Routing (Distance Vector and Link State)
- Spectrum Allocation
- Subnetting
- TCP Congestion Protocol
- TCP IP Basics
- Traffic Policing and Shaping
- Transmission Modes
- Virtual Lan
- Data link Layer
  Data link Layer
- Physical Layer
  Physical Layer
  - Introduction
Computer Security
Computer Security
DBMS
DBMS
DBMS Components
DBMS Components
DBMS Theory
DBMS Theory
- Notes
- SQL
DSA
DSA
Devops
Devops
- Bash
- Makefile
- Roadmap
Docker
Docker
Financial Markets
Financial Markets
Flutter
Flutter
Java
Java
Machine Learning
Machine Learning
- Decision Trees
  Decision Trees
  - Decision Trees
- Deep Learning
  Deep Learning
  - Deep Learning
  - Neural Network
Network Security
Network Security
OOPS
OOPS
- C++ OOP Interview Guide
OS
OS
OS Lab
OS Lab
- Preparation
- Pseudocode
- Data Structures
  Data Structures
  - Stage 24
    Stage 24
    
    File Status Table
    
    Open File Table
  - Stage 2
    Stage 2
    
    Data Free List
    
    Inode Table
    
    Root File
    
    User Table
  - Stage 9
    Stage 9
    
    Per Process Resource Table
    
    Process Table
    
    System Status Table
    
    User Area
- Stages
  Stages
  - Stage 10
  - Stage 11
  - Stage 12
  - Stage 13
  - Stage 14
  - Stage 15
  - Stage 16
  - Stage 17
  - Stage 18
  - Stage 19
  - Stage 2
  - Stage 20
  - Stage 21
  - Stage 22
  - Stage 23
  - Stage 24
  - Stage 25
  - Multi User Expansion
  - Pager Module
  - Stage 28
  - Stage 3
  - Stage 4
  - XSM Debugging
  - Running a user program
  - Stage 7
  - Stage 8
  - Handling Kernel Stack
- Theory
  Theory
RISC V
RISC V
SQL
SQL
- SQL Commands
Software Engineering
Software Engineering
- OOPS
- Software Requirements Specification
- Design Patterns
  Design Patterns
- Post MidSem
  Post MidSem
- Process Models
  Process Models
- Requirements Modelling
  Requirements Modelling
- Software Design
  Software Design
  - Class Diagram and Class Relationships
  - Software Design
  - Relationships
    Relationships
    
    Aggregation
    
    Association
    
    Composition
    
    Dependency
    
    Inheritance
System Design
System Design
- System Design
eBPF
eBPF
- Introduction

XSM Debugging

./xsm --debug

reg	Contents of registers
mem 1	Contents of memory page 1
s	Step to next instruction
c	Continue until next BRKP

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