Makefile

target: dependencies
    commands

hello.o: hello.c
    gcc -c hello.c

calc: main.o add.o sub.o
    gcc main.o add.o sub.o -o calc

main.o: main.c
    gcc -c main.c
add.o: add.c
    gcc -c add.c
sub.o: sub.c
    gcc -c sub.c

Variables

CC=gcc
CFLAGS=-Wall -g
OBJ = main.o add.o sub.o

calc: $(OBJ)
    $(CC) $(CFLAGS) $(OBJ) -o calc

Pattern Rules

CC = gcc
CFLAGS = -Wall -g
OBJ = main.o add.o sub.o 

calc: $(OBJ)
    $(CC) $(CFLAGS) $(OBJ) - o $@
%.o: %.c
    $(CC) $(CFLAGS) -c $<

Clean Rule

clean:
    rm -f *.o calc

Variable	Meaning
$@	The target file name
$<	The first prerequisite
$^	All prerequisites
$?	Only prerequisites newer than the target
### Phony Target

• Targets like clean don't produce real files

.PHONY: clean
clean:
    rm -f *.o calc

Multi Directory Project

src/ main.c math/ add.c sub.c include/ add.h sub.h

CC = gcc
CFLAGS = -Iinclude -Wall
SRC = src/main.c src/math/add.c src/math/sub.c
OBJ = $(SRC:.c=.o)
TARGET = calc 
$(TARGET): $(OBJ)
    $(CC) $(CFLAGS) -o $@

%.o: %.c
    $(CC) $(CFLAGS) -c $< -o $@
.PHONY: clean
clean:
    rm -f $(OBJ) $(TARGET)

MSG smitha HI THERE MACHA