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This attack exploits the Branch Predictor in CPU, which predicts the direction of each branch to save computation. If the predicted direction is wrong, it reverts the architectural register state but does not evict the associated cache lines, causing the attacker to execute Flush+Reload or Evict+Reload attack.

Spectre Vulnerability Variants

Spectre vulnerabilities trick modern CPU microarchitectures into speculatively executing unintended instruction sequences, causing transient microarchitectural side effects that leak confidential data across process, privilege, and isolation boundaries.

Variant 1: Bounds Check Bypass (CVE-2017-5753)

Core Mechanism

Variant 1 targets conditional branches that gate access to memory, such as if (x < array1_size) validation checks. It exploits the CPU's Pattern History Table (PHT) and Branch History Table (BHT).

Step-by-Step Execution

  1. Mistraining: The attacker repeatedly calls a vulnerable code path using valid, in-bounds indices (x < array1_size). This trains the branch predictor to expect the condition to evaluate to true.
  2. Memory Stall: The attacker flushes array1_size from the CPU cache using instructions like clflush, creating a memory latency delay (~200+ cycles) when the condition is next evaluated.
  3. Speculative Access: The attacker supplies an out-of-bounds index x_malicious pointing to secret data. While waiting for array1_size to read from DRAM, the CPU speculatively assumes the branch is true and executes the body of the if statement.
  4. Transient Leak: The speculative code loads the secret byte k = array1[x_malicious] and uses k to compute an address in a second array (array2[k * 4096]), loading that cache line into memory.
  5. Rollback & Extraction: The CPU completes the branch check, detects the misprediction, and discards all architectural register changes. The attacker then uses a cache timing attack (e.g., Flush+Reload) across array2 to measure access times; the cache line corresponding to k * 4096 responds quickly, revealing the secret byte value.
// Vulnerable Code Pattern
if (x < array1_size) {
    uint8_t secret = array1[x];
    uint8_t val = array2[secret * 4096];
}

Variant 2: Branch Target Injection (CVE-2017-5715)

Core Mechanism

Variant 2 targets indirect branches (jmp [reg], call [mem], ret) where the destination address is determined dynamically at runtime. It targets the Branch Target Buffer (BTB), a shared hardware cache responsible for predicting indirect branch target addresses.

Step-by-Step Execution

  1. Gadget Identification: The attacker identifies a sequence of instructions (a "Spectre gadget") mapped inside the victim's address space (e.g., within libc or kernel code) that reads memory and accesses a secondary buffer.
  2. BTB Poisoning: Because BTB entries index branches using a truncated subset of virtual address bits (address aliasing), the attacker executes indirect branches in their own user-space process at an address that maps to the same BTB slot as the victim's target branch. The attacker trains the BTB to predict the gadget’s address as the branch destination.
  3. Triggering Execution: The victim executes an indirect branch whose actual destination pointer is flushed from the cache.
  4. Speculative Hijack: The CPU stalls on reading the real destination address, consults the poisoned BTB entry, and speculatively jumps directly to the Spectre gadget inside the victim's memory space.
  5. Exfiltration: The gadget speculatively reads victim memory, performs an access to a secondary memory array to modify the cache hierarchy, and is subsequently rolled back when the CPU discovers the misprediction. The attacker uses side-channel timing analysis to reconstruct the secret.
Attacker Process                        Victim Process
----------------                        --------------
0x...500: jmp rax                       0x...500: call [r12] (Stalled)
 (Trains BTB to point to Gadget)                     |
                                                     v (Speculative Jump)
                                        0x...A00: mov rax, [rdi] (Gadget)
                                                  shl rax, 12
                                                  mov rbx, [rsi + rax]

Variant 4: Speculative Store Bypass (CVE-2018-3639)

Core Mechanism

Variant 4 exploits the memory disambiguation hardware unit in modern CPUs. This unit attempts to predict whether a pending memory load instruction depends on an earlier, uncommitted memory store instruction.

Step-by-Step Execution

  1. Delayed Store: A store instruction (e.g., overwriting a pointer or sensitive value) is executed, but its destination memory address calculation is delayed due to an unresolved dependency.
  2. Speculative Bypass: A subsequent load instruction targets the same memory location. The memory disambiguator speculates that the load does not depend on the pending store and executes the load immediately.
  3. Stale Data Read: The CPU speculatively loads stale, obsolete, or uninitialized data from memory instead of waiting for the updated store value.
  4. Transient Pipeline Leak: The transient pipeline processes this stale value (such as an old memory pointer to sensitive data) and feeds it into subsequent operations that alter the CPU cache state before the hardware detects the dependency and re-executes the load sequentially.
; Conceptual Variant 4 sequence
MOV [rax], rbx     ; Store operation (rax address calculation is delayed)
MOV rdx, [rcx]     ; Load operation (speculatively bypasses store, reading old data)
MOV r8, [rdx]      ; Dependent load that pulls memory into cache based on stale pointer

Microarchitectural Variations

Spectre-RSB (Return Stack Buffer)

  • Mechanism: Targets the Return Stack Buffer (RSB), a hardware stack designed specifically to predict return addresses from ret instructions.
  • Exploitation: Attackers use deep call stacks, function recursions, or context switches to cause an RSB underflow. When underflow occurs, the CPU falls back to BTB predictions, enabling attackers to hijack speculative control flow on return instructions using BTB poisoning.

Spectre-BHB (Branch History Injection)

  • Mechanism: Attacks systems with hardware mitigations like Intel eIBRS or ARM CSV2 that isolate BTB entries across privilege boundaries.
  • Exploitation: Although BTB entries are isolated, processors still share global Branch History Buffers (BHB) that track historical execution paths. Attackers execute precise sequences of branches in user mode to manipulate global BHB history, inducing mispredictions in the victim/kernel space despite BTB isolation.